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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories
Data Sheet
FEATURES:
* Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 * 2.7-3.6V Read Operation * Superior Reliability - Endurance: At least 1000 Cycles - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 10 mA (typical) - Standby Current: 2 A (typical) * Fast Read Access Time: - 70 ns - 90 ns * Latched Address and Data * Fast Byte-Program Operation: - Byte-Program Time: 10 s (typical) - Chip Program Time: 0.6 seconds (typical) for SST37VF512 1.2 seconds (typical) for SST37VF010 2.4 seconds (typical) for SST37VF020 4.8 seconds (typical) for SST37VF040 * Electrical Erase Using Programmer - Does not require UV source - Chip-Erase Time: 100 ms (typical) * CMOS I/O Compatibility * JEDEC Standard Byte-wide Flash EEPROM Pinouts * Packages Available - 32-pin PLCC - 32-pin TSOP (8mm x 14mm) - 32-pin PDIP
PRODUCT DESCRIPTION
The SST37VF512/010/020/040 devices are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable (MTP), low cost flash, manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST37VF512/010/020/040 can be electrically erased and programmed at least 1000 times using an external programmer, e.g., to change the contents of devices in inventory. The SST37VF512/010/020/040 have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide flash memories. Featuring high performance Byte-Program, the SST37VF512/010/020/040 provide a typical Byte-Program time of 10 s. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST37VF512/010/020/040 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST37VF512/010/020/040 are offered in 32-pin PLCC, TSOP and PDIP packages. See Figures 1, , 2, and 3 for pinouts.
Device Operation
The SST37VF512/010/020/040 devices are nonvolatile memory solutions that can be used instead of standard flash devices if in-system programmability is not required. It is functionally (Read) and pin compatible with industry standard flash products.The device supports electrical Erase operation via an external programmer.
Read
The Read operation of the SST37VF512/010/020/040 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming the CE# pin has been low and the addresses have been stable for at least TCE - TOE. When the CE# pin is high, the chip is deselected and a standby current of only 10 A (typical) is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is VIH. Refer to Figure 4 for the timing diagram.
(c)2001 Silicon Storage Technology, Inc. S71151-02-000 5/01 397 1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
Byte-Program Operation
The SST37VF512/010/020/040 are programmed by using an external programmer. The programming mode is activated by asserting 12V (5%) on OE# pin and VIL on CE# pin. The device is programmed using a single pulse (WE# pin low) of 10 s per byte. Using the MTP programming algorithm, the Byte-Program process continues byte-bybyte until the entire chip has been programmed. Refer to Figure 10 for the flowchart and Figure 6 for the timing diagram.
Product Identification Mode
The Product Identification mode identifies the devices as SST37VF512, SST37VF010, SST37VF020, and SST37VF040 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode, the programming equipment must force VH (12V5%) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation. TABLE 1: PRODUCT IDENTIFICATION
Chip-Erase Operation
The only way to change a data from a "0" to "1" is by electrical erase that changes every bit in the device to "1". The SST37VF512/010/020/040 use an electrical Chip-Erase operation. The entire chip can be erased in 100 ms (WE# pin low). In order to activate erase mode, the 12V (5%) is applied to OE# and A9 pins while CE# is low. All other address and data pins are "don't care". The falling edge of WE# will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figure 9 for the flowchart and Figure 5 for the timing diagram.
Manufacturer's ID Device ID SST37VF512 SST37VF010 SST37VF020 SST37VF040
Address 0000H 0001H 0001H 0001H 0001H
Data BFH C4H C5H C6H C2H
T1.2 397
Design Considerations
The SST37VF512/010/020/040 should have a 0.1F ceramic high frequency, low inductance capacitor connected between VDD and GND. This capacitor should be placed as close to the package terminals as possible. OE# and A9 must remain stable at VH for the entire duration of an Erase operation. OE# must remain stable at VH for the entire duration of the Program operation.
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffer Y-Decoder
CE# OE# A9 WE#
Control Logic
I/O Buffers DQ7 - DQ0
397 ILL B1.1
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
SST37VF512 SST37VF010 SST37VF020 SST37VF040
WE# WE# WE# WE#
VDD
A12
A15
A16
A18
VDD
A12
A15
A16
VDD
A12
A15
A16
NC
VDD
A12
A15
NC
NC
SST37VF040 SST37VF020 SST37VF010 SST37VF512 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A7 A6 A5 A4 A3 A2 A1 A0 DQ0
NC SST37VF512 SST37VF010 SST37VF020 SST37VF040
5 6 7 8 9 10 11 12 13 SST37VF040 SST37VF020 SST37VF010 SST37VF512
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
NC
A17
NC
A17
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
32-pin PLCC Top View
21 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
397 ILL F02a.2
DQ1
DQ2
VSS
DQ3
DQ4
DQ5 DQ5 DQ5
DQ1
DQ2
VSS
DQ3
DQ4
DQ1
DQ2
VSS
DQ3
DQ4
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC
SST37VF040 SST37VF020 SST37VF010 SST37VF512
A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
DQ6
DQ6
DQ6
SST37VF512 SST37VF010 SST37VF020 SST37VF040
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
397 ILL F01.0
Standard Pinout Top View
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM
(c)2001 Silicon Storage Technology, Inc.
X
14MM)
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
SST37VF040 SST37VF020 SST37VF010 SST37VF512 A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
SST37VF512 SST37VF010 SST37VF020 SST37VF040 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
397 ILL F02b.1
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP TABLE 2: PIN DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 CE# WE# OE# VDD VSS NC Pin Name Address Inputs Data Input/output Chip Enable Write Enable Output Enable Power Supply Ground No Connection Unconnected pins.
T2.1 397
Functions To provide memory addresses. To output data during Read cycles and receive input data during Program cycles. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To program or erase (WE# = VIL pulse during Program or Erase) To gate the data output buffers during Read operation when low To provide 3.0V supply (2.7-3.6V)
1. AMS = Most significant address AMS = A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet TABLE 3: OPERATION MODES SELECTION
Mode Read Output Disable Standby Chip-Erase Byte-Program Program/Erase Inhibit Product Identification CE# VIL VIL VIH VIL VIL X X VIL WE# VIH X X VIL VIL VIH X VIH A9 AIN X X VH AIN X X VH OE# VIL VIH X VH VH X VIL or VIH VIL DQ DOUT High Z High Z High Z DIN High Z High Z/ DOUT Manufacturer's ID (BFH) Device ID1 Address AIN AIN X X AIN X X AMS2 - A1 = VIL, A0 = VIL AMS2 - A1 = VIL, A0 = VIH
T3.1 397
1. Device ID = C4H for SST37VF512, C5H for SST37VF020, C6H for SST37VF020, and C2H for SST37VF040 2. AMS = Most significant address AMS = A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040 Note: X = VIL or VIH (or VH in case of OE# and A9) VH = 12V5%
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Ambient Temp 0C to +70C VDD 2.7-3.6V
AC CONDITIONS
OF
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figures 7 and 8
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet TABLE 4: READ MODE DC OPERATING CHARACTERISTICS VDD=2.7-3.6V (Ta = 0C to +70C (Commercial))
Limits Symbol IDD Parameter VDD Read Current 12 ISB ILI ILO VIL VIH VIHC VOL VOH IH Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage Supervoltage Current for A9 for Read-ID VDD-0.3 200 0.7 VDD VDD-0.3 0.2 15 1 10 0.8 mA A A A V V V V V A Min Max Units Test Conditions Address input=VIL/VIH, at f=1/TRC Min VDD=VDD Max CE#=OE#=VIL, all I/Os open CE#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min CE#=OE#=VIL, A9=VH Max
T4.3 397
TABLE 5: PROGRAM/ERASE DC OPERATING CHARACTERISTICS VDD=2.7-3.6V
Limits Symbol Parameter IDD ILI ILO VH IH VDD Erase or Program Current Input Leakage Current Output Leakage Current Supervoltage for A9 and OE# Supervoltage Current for A9 and OE# Min Max Units Test Conditions 20 1 10 11.4 12.6 200 mA A A V A
(Ta = 25C5C)
CE#=VIL, OE#=VH, VDD=VDD Max, WE#=VIL VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max OE#=VH Max, A9=VH Max, VDD=VDD Max, CE# = VIL
T5.1 397
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units s s
T6.1 397
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE
Parameter CI/O
1
(Ta = 25C, f=1 Mhz, other pins open)
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T7.0 397
CIN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T8.3 397
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
AC CHARACTERISTICS
TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
(Ta = 0C to +70C (Commercial))
SST37VF512-70 SST37VF010-70 SST37VF020-70 SST37VF040-70 Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 0 0 0 30 30 Min 70 70 70 35 Max
SST37VF512-90 SST37VF010-90 SST37VF020-90 SST37VF040-90 Min 90 90 90 45 0 0 30 30 0 Max Units ns ns ns ns ns ns ns ns ns
T9.2 397
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD = 2.7-3.6V (Ta = 25C5C)
Symbol TBP TCES TCEH TAS TAH TDS TDH TPRT TVPS TVPH TPW TEW TVR TART TA9S TA9H Parameter Byte-Program Time CE# Setup Time CE# Hold Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE# Rise Time for Program and Erase OE# Setup Time for Program and Erase OE# Hold Time for Program and Erase WE# Program Pulse Width WE# Erase Pulse Width OE#/A9 Recovery Time for Erase A9 Rise Time to 12V during Erase A9 Setup Time during Erase A9 Hold Time during Erase Min 12 1 1 1 1 1 1 1 1 1 10 100 1 1 1 1 15 500 Max 20 Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
T10.0 397
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
TRC ADDRESS
TAA
CE#
TCE
OE# VIH WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TCLZ
TOH DATA VALID
397 ILL F03.0
FIGURE 4: READ CYCLE TIMING DIAGRAM
ADDRESS (EXCEPT A9) CE#
TCEH
DQ7-0 VH VDD VSS VH A9 VIH VIL TART TA9H WE# TCES
397 ILL F04.0
TVPS TVPH TPRT TVR TA9S
OE#
TEW
FIGURE 5: CHIP-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
TPC
ADDRESS
ADDRESS VALID
TAH
CE#
TAS
TCEH
TDS TDH
DQ7-0
HIGH-Z VH VDD
DATA VALID
TVPS TPRT
OE#
VSS
TPW TVPH
WE#
TCES
397 ILL F05.0
FIGURE 6: BYTE-PROGRAM TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
397 ILL F06.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 V) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 7: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
397 ILL F07.1
FIGURE 8: A TEST LOAD EXAMPLE
(c)2001 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
Start
A9 = VH, OE# = VH
CE# = VIL Erase 100ms pulse (WE# = VIL)
WE# = VIH
OE#/A9 = VIL or VIH
Wait TVR Recovery Time
Read Device
Compare all bytes to FF Yes
No
Device Passed
Device Failed
397 ILL F08.0
FIGURE 9: CHIP-ERASE ALGORITHM
(c)2001 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
Start
Erase*
OE# = VH
Address = First Location; Load Data
CE# = VIL
Program 10s pulse (WE# = VIL)
Increment Address No
Last Address? Yes
OE# = VIL
Wait TVR
Read Device
Compare all bytes to original data Yes
No
Device Passed
Device Failed
397 ILL F09.1
*See Figure 9
FIGURE 10: BYTE-PROGRAM ALGORITHM
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet Device SST37VFxxx Speed - XXX Suffix1 XX Suffix2 XX Package Modifier H= 32 pins Numeric = Die modifier Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) P = PDIP Operating Temperature C = Commercial = 0 to +70C Minimum Endurance 3= 1000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Device Density 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit
SST37VF512 Valid combinations SST37VF512-70-3C-NH SST37VF512-90-3C-NH SST37VF512-70-3C-WH SST37VF512-90-3C-WH SST37VF512-90-3C-PH
SST37VF010 Valid combinations SST37VF010-70-3C-NH SST37VF010-90-3C-NH SST37VF010-70-3C-WH SST37VF010-90-3C-WH SST37VF010-90-3C-PH
SST37VF020 Valid combinations SST37VF020-70-3C-NH SST37VF020-90-3C-NH SST37VF020-70-3C-WH SST37VF020-90-3C-WH SST37VF020-90-3C-PH
SST37VF040 Valid combinations SST37VF040-70-3C-NH SST37VF040-90-3C-NH
Example:
SST37VF040-70-3C-WH SST37VF040-90-3C-WH
SST37VF040-90-3C-PH
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
.485 .495 .447 .453 .042 .048
2 1 32
SIDE VIEW
.106 .112 .020 R. MAX. .023 x 30 .029 .030 R. .040
BOTTOM VIEW
Optional Pin #1 Identifier
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400 BSC
.490 .530
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32.PLCC.NH-ILL.2 4. Coplanarity: 4 mils.
32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
Pin # 1 Identifier
1.05 0.95 .50 BSC
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
32.TSOP-WH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH
X
14MM
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397
14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
32
C L
.600 .625
Pin #1 Identifier
.065 .075
1
1.645 1.655 7 4 PLCS.
.530 .550
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600 BSC
0 15
.070 .080
.045 .065
.016 .022
.100 BSC
Note:
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32.pdipPH-ILL.2
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH
(c)2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
397
15
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com
(c)2001 Silicon Storage Technology, Inc. S71151-02-000 5/01 397
16

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